### A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

#### Abstract

*W*range of 3 to 35 Âµm the average

_{P}*W*/

_{N}*W*ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

_{P}#### Keywords

#### Full Text:

PDF#### References

Y. Fan, Y. Huijing and L. Gang, â€œA 4th-order Switch-capacitor Low-pass Filter for Quartz Gyroscope Interface Circuit,â€ TELKOMNIKA, Vol. 11, No. 10, pp. 5718-5724, 2013.

Y. Fan, Y. Huijing and L. Gang, â€œA High-Performance Sigma-Delta ADC for Audio Decoder Chip,â€ TELKOMNIKA, Vol. 11, No. 11, pp. 6570-6576, 2013.

B.J. Sheu, J.H. Shieh, and M. Patil, â€œModeling charge injection in MOS analog switches,â€ IEEE Transactions on Circuits and Systems, vol. CAS-34, no. 2, pp. 214-216, 1987.

B.J. Sheu and C. Hu, â€œSwitch-induced error voltage on a switched capacitor,â€ IEEE Journal of Solid-State circuits, vol. SC-19, no. 4, pp. 519-525, 1984.

G. Wegmann and E. Vittoz, and F. Rahali, â€œCharge injection in analog MOS switches,â€ IEEE Journal of Solid-State Circuits, vol. SC-22, no. 6, pp. 1091-1097, 1987.

J.H. Shieh, M. Patil, and B J. Sheu, â€œMeasurement and analysis of charge injection in MOS analog switches,â€ IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 277-281, Apr. 1987.

Y.B. Gu and M.J. Chen, â€œA new quantitative model for weak inversion charge injection in MOSFET analog switches,â€ IEEE Transactions on Electron Devices, vol. 43, no. 2, pp. 295-301, 1996.

A. Danchiv, M. Bodea, â€œA New Simplified Model for Charge Injection Induced Sample and Hold Error,â€ 15th IEEE Mediterranean Electrotechnical Conference MELECON 2010, pp.743-748. 2010.

P. Torkzadeh and M. Atarodi, â€œChannel Charge Injection analysis and its modeling in z-domain for switched-capacitor integrators,â€ 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, pp. 126-129, 2009.

P. Torkzadeh, M. Atoradi, â€œBehavioral Modeling of Clock Feed-Through and Channel Charge Injection NonIdeal Effects in SIMULINK for Switched-Capacitor Integrator,â€ Elsevier Simulation Modelling Practice and Theory 18, pp.483-499, 2009.

W. Xu, G. Friedman, â€œClock Feedthrough in CMOS Analog Transmission Gate Switches,â€ Springer Analog Integrated Circuits and Signal Processing, 44, 271-281, 2005.

B. Razavi, â€œDesign of analog CMOS integrated circuits,â€ McGraw-Hill, 2001.

R. C. Yen, P. R. Gray, â€œA MOS switched-capacitor instrumentation amplifier,â€ IEEE Journal of Solid-State Circuits, 17 (6), pp. 1008â€“1013, 1982.

A. Abolhasani, M. Tohidi, K. Hadidi, A. Khoei, â€œA new high-speed, high-resolution open-loop CMOS sample and hold,â€ Analog Integrated Circuits and Signal Processing, 78 (2), pp. 409â€“419, 2014.

T. Moradi Khanshan, M. Nematzade, K. Hadidi, A. Khoei, Z. D. Koozehkanani, J. Sobhi, â€œVery linear open-loop CMOS sample-and-hold structure for high precision and high-speed ADCs,â€ Analog Integrated Circuits and Signal Processing, 88 (1), pp. 23â€“30, 2016.

M. Mousazadeh, â€œA highly linear open-loop high-speed CMOS sample and hold,â€ Analog Integrated Circuits and Signal Processing, 90 (3), pp. 703â€“710, 2017.

T. Nonthaputha, M. Kumngern, S. Lerkvaranyu, â€œCMOS sample-and-hold circuit using current conveyor analog switch,â€ in 2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 1â€“4, 2016.

L. Mountrichas, S. Siskos, â€œA high-speed offset canceling distributed sample-and-hold architecture for flash A/D converters,â€ Microelectronics Journal, 44 (12), pp. 1123-1131, 2013.

K. Ding, K. Cai, Y. Han, â€œDesign of a high-speed sample-and-hold circuit using a substrate-biasing-effect attenuated T switch,â€ Microelectronics Journal, 41 (12), pp. 809â€“814, 2010

P. Pouya, A. Ghasemi, H. Aminzadeh, â€œA low-voltage high-speed high linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits,â€ in 2015 2nd International Conference on Knowledge-Based Engineering and Innovation (KBEI), pp. 418â€“421, 2015.

T. B. Nazzal, S. A. Mahmoud, â€œLow-power bootstrapped sample and hold circuit for analog-to-digital converters, in: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1â€“4, 2016.

DOI: http://dx.doi.org/10.18517/ijaseit.8.3.4329

### Refbacks

- There are currently no refbacks.

Published by INSIGHT - Indonesian Society for Knowledge and Human Development