A New Approach for Designing of Computer Architectures Using Multi-Value Logic

Alessandro Simonetta, Maria Cristina Paoletti, Maurizio Muratore


In the last decade, we have seen how Moore's law has lost its validity because it has reached the physical limit of miniaturization of components and the problem of thermal dissipation increasing with the chip’s clock frequency. For this reason, multi-core architectures were born, and quantum computing is being looked at as a possible solution for more computing power. The aim of this article is to demonstrate the possibility to realize computer architectures using multi-value logic. The objective is reached when we are able to translate any MVL function into the corresponding MVL circuit. The method proposed is completely independent of the basis adopted in the MVL domain and the physical quantity used to represent or transfer the domain values. Thus, this approach provides a new theoretical and practical context for applying new technologies or polymorphic materials, which can represent multiple values. In order to give concreteness to the analyzed theoretical aspects, we will represent a case study based on a classical combinational circuit, the summing circuit using LTspice® XVII (© Analog Device Corporation) as simulation environment has been carried out. The results show that it is possible to build MVL combinatorial circuits, although there are limitations because the proposed solution is just a proof of concept. The method can also be successfully applied to sequential MVL circuits, which are not the subject of the present article.


multi-valued logic; computer architecture; linear algebra; digital circuits; combinatorial circuit

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F. Silvestri, S. Acciarito, G. C. Cardarilli, G. M. Khanal, L. D. Nunzio, R. Fazzolari, M. Re, Fpga implementation of a low-power qrs extractor, volume 512, 2019. doi:10.1007/978-3-319-93082-4_2.

G. C. Cardarilli, L. D. Nunzio, R. Fazzolari, M. Re, Fine-grain reconfigurable functional unit for embedded processors, 2011. doi:10.1109/ACSSC.2011. 6190048.

D. Giardino, G. C. Cardarilli, L. D. Nunzio, R. Fazzolari, A. Nannarelli, M. Re, S. Spano, M-psk demodulator with joint carrier and timing recovery, IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2021). doi:10.1109/TCSII.2020.3041342.

G. C. Cardarilli, L. D. Nunzio, R. Fazzolari, D. Giardino, M. Matta, M. Patetta, M. Re, S. Spanò, Approximated computing for low power neural networks, Telkomnika (Telecommunication Computing Electronics and Control) 17 (2019). doi:10.12928/TELKOMNIKA.v17i3.12409.

Z. T. Sandhie, J. A. Patel, F. U. Ahmed, M. H.Chowdhury, Investigation of multiple-valued logic technologies for beyond-binary era, ACM Comput. Surv. 54 (2021). doi:10.1145/3431230.

B. S. Raghavan, V. S. K. & Bhaaskaran, Design of novel Multiple Valued Logic (MVL) circuits, International Conference on Nextgen Electronic Technologies: Silicon to Software, (2017) 371-378. doi:10.1109/ICNETS2.2017.8067963.

B. Cambou, P. Flikkema, J. Palmer, D. Telesca, C. Philabaum, Can ternary computing improve information assurance? Cryptography 2 (2018) 6. doi:10.3390/cryptography2010006.

D. Etiemble, Evolution of technologies and multi-valued circuits, ArXiv abs/1907.01451 (2019).

S. N. Shah, Addressing the interpretability problem for deep learning using many valued quantum logic (2020). arXiv: 2007.01819.

R. Wang, J.-Q. Yang, J.-Y. Mao, Z.-P. Wang, S. Wu, M. Zhou, T. Chen, Y. Zhou, S.-T. Han, Recent advances of volatile memristors: Devices, mechanisms, and applications, Advanced Intelligent Systems 2 (2020). doi:10.1002/aisy.202000055.

M. Huang, X. Wang, G. Zhao, P. Coquet, B. Tay, Design and implementation of ternary logic integrated circuits by using novel two-dimensional materials, Applied Sciences 9 (2019). doi:10.3390/app9204212.

A. Maksim C. Jae-Woong, K.Jiwan, K. Hyeongjun, J. Sooyoung, K. Kwan-Ho, P. Jin-Hong, Negative differential transconductance device with a stepped gate dielectric for multi-valued logic circuits, Nanoscale Horizons, 10 (2020) 1378-1385. doi: 10.1039/D0NH00163E.

A. Esin, Analysis and design principles of modern control systems based on multi-valued logic models, Upravlenie Bol'shimi Sistemami 88 (2020) 69–98, doi:10.25728/ubs.2020.88.4.

Z. Sun, G. Pedretti, E. Ambrosi, A. Bricalli, W. Wang and D. Ielmini, Solving matrix equations in one step with cross-point resistive arrays, Proceeding of the National Academy of Sciences of the United States of America 116 (2019). doi:10.1073/pnas.1815682116.

M. Jhamb, R. Mohan, Ultra low power design of multi-valued logic circuit for binary interfaces, Journal of King Saud University - Computer and Information Sciences (2021). doi:10.1016/j.jksuci.2021.01.010.

L. Lee, J. Hwang, J. W. Jung, J. Kim, H. I. Lee, S. Heo, M. Yoon, S. Choi, N. V. Long, J. Park, J. W. Jeong, J. Kim, K. R. Kim, D. H. Kim, S. Im, B. H. Lee, K. Cho, M. M. Sung, Zno composite nanolayer with mobility edge quantization for multi-value logic transistors, Nature Communications 10 (2019). doi:10.1038/ s41467-019-09998-x.

A. Simonetta, M. C. Paoletti, Designing digital circuits in multi-valued logic, International Journal on Advanced Science, Engineering and Information Technology 8 (2018) 1166-1172. doi:10.18517/ijaseit.8.4. 5966.

O. Krestinskaya, B. Choubey, A. P. James, Memristive gan in analog, Scientific Reports 10 (2020). doi:10.1038/s41598-020-62676-7.

D. Bhattacharjee, W. Kim, A. Chattopadhyay, R. Waser, V. Rana, Multi-valued and fuzzy logic realization using TaOx memristive devices, Scientific Reports 8 (2018) 8. doi:10.1038/s41598-017-18329-3.

S. B. Jo, J. Kang, J. Cho, Multi-valued logic gates: Recent advances on multi-valued logic gates: A materials perspective, Advanced Science 8 (2021). doi:10.1002/advs.202170040.

DOI: http://dx.doi.org/10.18517/ijaseit.11.4.15778


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