A Methodology for Cell Merging Circuit Transformation on Post-placement High Speed Design

Diana Tan Hui Lyn, Arjuna Marzuki, Jennifer Lim Min May


This paper proposes a localize circuit transformation algorithm to further optimize the post-placement netlist in order to improve the overall timing of a design. The proposed algorithm reduces the total cell delay and net delay of timing violation paths by replacing a small group of cells (form up by two to three cells) that are placed close to each other with a functional equivalent standard cell available in the technology library. The algorithm has been implemented and applied to a number of optimized postplacement netlists which have went through conventional post-placement circuit transformation optimization processes such as gate relocation, cell re-sizing, repeater insertion and cell replication. The experimental results show that on average, this algorithm is able to further improve the timing of the optimized post-placement netlist by 27.75%, while keeping the design area increase by 0.2%.


post-placement optimization; cell merging; circuit transformation; netlist optimization; timing closure

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DOI: http://dx.doi.org/10.18517/ijaseit.2.1.143


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Published by INSIGHT - Indonesian Society for Knowledge and Human Development