A Fast AES Hardware Security Module for Internet of Things Applications

Minyoung Lee, HyunSeo Lim, Yoojeong Yang, Sunhee Kim


As the Internet of Things is used in various fields, Internet of Things security has become important. Since most Internet of Things devices is implemented as embedded systems, they provide a software-implemented encryption algorithm. Most embedded systems use relatively low-performance CPUs and the software processes data serially, making it difficult to process complex security algorithms in real-time. Therefore, it is necessary to have a stable encryption module with less impact on system performance. In this paper, we designed an AES hardware security module. Because it is implemented with dedicated hardware, it can process a strong encryption algorithm in real time without affecting the performance of the system. The proposed AES hardware module is designed using Verilog-HDL, tested in ModelSim and implemented in Altera FPGA Cycloneâ…£. The designed AES hardware adopts parallel processing technique and pipeline structure considering the computational complexity and processing order of the algorithm. As a result, it is faster than AES modules implemented in software. In addition, its latency was reduced to about 280 ns, which is about 16 % of the latency of the previous AES hardware module. Not only did the performance improve, but the number of logic elements and registers also decreased to 83.6% and 92.8%, respectively. The proposed AES hardware module is verified by applying it to a door lock system and is expected to be applied to various Internet of Things devices.


AES; Encryption; Internet of Things; security

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DOI: http://dx.doi.org/10.18517/ijaseit.10.4.12760


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